This application claims priority to Japanese Patent Application No. JP 2000-290259, and the disclosure of that application is incorporated herein by reference to the extent permitted by law.
1. Field of the Invention
The present invention relates to a method for producing a semiconductor device, particularly to a method for producing a semiconductor device utilizing an interlayer insulating film of fluorine doped silicon oxide having a low dielectric constant.
2. Description of the Related Art
Recently, miniaturization and utilization of multilevel interconnection in a device structure are advanced further to respond to the rising needs for higher order of integration and multifunction in a semiconductor device. Such advancement of the semiconductor device is causing serious problems such as signal delay or larger power consumption due to an increase of wiring capacity. To countermeasure the problems, a dual damascene wiring forming technology is introduced. The dual damascene wiring forming technology enables to use copper (Cu) of a low resistance material for wiring material. However, the technology has an shortcoming. That is, an additional investment for building new infrastructure is required to carry out the dual damascene wiring forming technology, and a manufacturing cost may be increased.
Alternatively, the following method shown in FIG. 6 is suggested. In the method, a low dielectric constant material is utilized as an interlayer insulating film 3 to fill gaps between wiring 2 formed on a substrate 1. Fluorine-containing silicon oxide (so called fluorinated silicate glass (FSG)) or polyimide-series organic resin may be considered as a candidate for the low dielectric constant insulation film material. Particularly, the FSG layer is a promising material to realize lower cost production because that (1) the FSG layer can be formed by utilizing a widely-used plasma chemical vapor deposition (CVD) apparatus for forming silicon oxide film and (2) the FSG layer is comparably easy to switch with a silicon oxide film in a process for forming interlayer insulating film.
However, quality of the FSG layer deteriorates due to moisture absorption as fluorine concentration increases so as to lower the dielectric constant thereby a metal wiring film formed at the upper part are tend to be flaked off. As a way to prevent such things happen, Japanese Patent Publication No. JP 07-29975, JP 07-74245 disclose a method to prevent the moisture absorption of the FSG layer by forming a layer of a silicon oxide film on the FSG layer.
The FSG layer is formed at a low temperature equal or less than 500xc2x0 C. while being heated with plasma-assisted heating. Accordingly, undesirable impurities such as hydrogen and defects such as unstable Sixe2x80x94Fx bonding (called free species hereafter), that are generated in plasma during the film forming process, may tend to be incorporated into the film. It is known that the free species incorporated in the film desorbs during a formation process of the metal wiring film thereby causing flaking-off of the metal wiring film. Accordingly, it is desired to desorb the free species in the film by applying heat equal or more than the film forming temperature after the FSG layer formation.
When the interlayer insulating film covering the wiring is planarized as shown in FIG. 7, the following steps are performed. First, FSG film 3 is formed on the substrate 1 so as to cover wiring 2. Then, an insulation film 4 having superior planar property is formed on the FSG film 3. Finally, a chemical mechanical polishing (CMP) is performed on the insulation film 4. However, a structure of the film may change to cause, for example, desorption of fluorine from the FSG film 3 due to an reaction with the polishing slurry if the CMP advances to reach the FSG film 3 thereby causing deterioration of the film quality at exposed surface layer of the FSG film 3.
FIGS. 8-10 show graphs comparing changes in the film quality of the FSG layer before the CMP (as-deposited) and after the CMP. Here, the CMP is performed on the FSG layer with using polishing conditions for a typical silicon oxide wherein the FSG layer is formed by a parallel plate plasma CVD apparatus utilizing film forming gas of tetraethoxy silane (TEOS)/oxygen(O2)/ethan hexafluoride(C2F6). Sixe2x80x94F bond content at the vertical axis shown FIG. 8 indicates an area ratio of Sixe2x80x94F bond peak with respect to Sixe2x80x94O bond peak obtained by a FT-IR/ATR method. xe2x80x94OH bond content at the vertical axis shown FIG. 9 indicates an area ratio of xe2x80x94OH bond peak with respect to Sixe2x80x94O bond peak obtained by a FT-IR/ATR method.
As shown in FIG. 8, the Sixe2x80x94F bond content in the FSG layer is decreased after the CMP process. Further, as shown in FIG. 9, a bond content with hydroxyl group in the FSG layer is increased after the CMP process. Further, as shown in FIG. 10, both a refractive index and a relative dielectric constant of the FSG layer are increased after the CMP
It is contemplated that these observed changes (deterioration) are caused by hydrolysis of the Sixe2x80x94F bond due to moisture absorption of the FSG layer during the CMP process.
In order to prevent fluorine diffusion due to the deterioration of the FSG layer quality described above, JP application (Published) 10-26829 discloses a method for forming a silicon oxide film 6 as a cap layer on a polished surface generated by the CMP process thereby preventing the flaking-off of wiring formed on the FSG film 3 as shown in FIG. 11. However, there is possibility of losing the low dielectric constant effect in the FSG film 3 as described above in case that a part A having deteriorated film quality due to the CMP process extends down into the inside of the FSG layer. Accordingly, there is suggested another method for forming the cap layer of the silicon oxide film 6 after removing the deteriorated part A by sputtering after the CMP process.
However, in the methods of forming the silicon oxide film and adding the heating process after the FSG layer forming process to prevent the film flaking-off at the interlayer insulating film comprising the FSG among the above-cited production methods, the substrate is required to transfer between a film forming chamber of the FSG layer and a film forming chamber of the silicon oxide film, or, between a film forming chamber of the FSG layer and a heat processing chamber. These additional process may causes an increase of the production steps for the semiconductor device.
Further, the method utilizing the sputtering of the polished surface layer or the method for forming the silicon oxide layer on the polished surface after the CMP process may also cause an increase of production steps for the semiconductor device.
Accordingly, it is desired to provide a semiconductor device production method capable of forming a FSG layer with a better film quality without significantly increasing a number of process steps.
A semiconductor device production method in accordance with one embodiment of the present invention is a semiconductor device production method including a step for forming an interlayer insulating film having a fluorine-doped silicon oxide layer on a substrate. In a first method according to one embodiment of the present invention, a silicon oxide layer is formed after formation of a fluorine-doped silicone oxide layer in the same chamber of a plasma processing apparatus. The silicon oxide layer is formed on the fluorine-doped silicon oxide layer at temperature higher than a forming temperature of the fluorine-doped silicon oxide layer. The interlayer insulating film comprises these fluorine-doped silicon oxide layer and silicon oxide layer formed thereon.
According to the first method, the free species incorporated into the fluorine-doped silicon oxide layer during its formation may be desorbed from the fluorine-doped silicon oxide layer during the subsequent formation of the silicon oxide layer with a higher temperature than the forming temperature of the fluorine-doped silicon oxide layer. Furthermore, the formations of the fluorine-doped silicon oxide layer and the silicon oxide layer are performed continuously in the same chamber. Accordingly, it is not necessary to increase a number of the process steps as long as forming conditions of each films are modified accordingly.
In a second method according to one embodiment of the present invention, a surface layer of a fluorine-doped silicon oxide layer is removed by sputtering. The sputtering of the surface layer is subsequently performed after formation of the fluorine-doped silicon oxide layer. Both the formation of the fluorine-doped silicon oxide layer and the sputtering may be carried out in the same chamber of a plasma processing apparatus.
According to the second method, a low temperature annealing effect due to plasma energy may act on the fluorine-doped silicon oxide layer by sputtering the surface layer of the fluorine-doped silicon oxide layer. Accordingly, the free species incorporated into the fluorine-doped silicon oxide layer during its formation may be desorbed from the fluorine-doped silicon oxide layer during the sputtering process. Furthermore, it is not necessary to increase a number of the process steps as long as source gases and processing conditions are modified accordingly since the formation of the fluorine-doped silicon oxide layer and the sputtering are continuously carried out in the same chamber.